The present invention generally relates to inter-processor transmission systems, and more particularly to an inter-processor transmission system which has reduced load on the software.
The utilization limit of the multiprocessor system is rapidly expanding so as to share the load, distribute the functions and distribute the danger. In the multiprocessor system, the positive high-speed data transmission between the processors is an important factor.
As methods of realizing the positive high-speed data transmission between the processors, the following two methods are conventionally used. The two methods are the common memory system and the data link system.
The common memory system will be described in conjunction with FIG. 1. According to the common memory system, each processor can make access to a common memory. In FIG. 1, a processor 10 and a memory 11 are coupled via a bus 12, and a processor 20 and a memory 21 are coupled via a bus 22. A common memory 30 is coupled to the buses 12 and 22. Data are first written into the memory 11 under the control of the processor 10. Then, the processor 10 transfers the data to an address Ai of the common memory 30. The processor 20 reads the data from the address Ai of the common memory 30 and stores the data into the memory 22. The processors 10 and 20 need not necessarily operate in synchronism, but the processors 10 and 20 operate in sequence so that the processor 20 reads the data from the address Ai of the common memory 30 after the processor 10 writes the data which is stored in the memory 11 to the common memory 30 at the address Ai, and the processor 20 reads the data from the address Ai of the common memory 30 before the processor 10 writes the next data which is stored in the memory 11 to the common memory 30 at the address Ai.
However, the common memory system suffers problems in that the bus structure of the processor becomes complex and an exclusive control is necessary when making an access to the same memory region, thereby making the hardware structure complex. In addition, the coupling between the processors is an intimate coupling, and as a result, there are restrictions on the software of the processor since the address, sequence and the like of the access must be prearranged.
The data link system will be described in conjunction with FIG. 2. In FIG. 2, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. According to the data link system, the data transfer between the processors is made by use of a high-speed circuit or an inter-processor link. In FIG. 2, a transmitter 14 is coupled to the bus 12 and a receiver 24 is coupled to the bus 22. The transmitter 14 and the receiver 24 are coupled via a transmission line.
According to the data link system, the coupling between the processors is sparse because the transmission may be made at any time. However, the data link system suffers a problem in that the load on the software of the processor is large owing to the software control of the high-speed data transfer.